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The methods and systems relate to annealing of silicon wafers, and more particularly to compensating for anneal non-uniformities.
Following ion implantation in a silicon wafer, the dopant may be activated to provide the required electrical properties to the silicon. The dopant activation may be typically done by thermally cycling, or annealing, the wafer. The annealing process may be controlled to provide the required electrical properties including controlling the maximum temperature that the wafer may be subjected to, the time the wafer may be maintained at the maximum temperature and the rate or rates at which the temperature is raised and decreased.
In addition, control of the annealing process may serve to minimize deleterious effects, such as out-diffusion. Out-diffusion may result from dopant within the silicon diffusing to and eventually leaving the surface of the wafer. The rate of out-diffusion can be dependent on temperature. Also, the dopant concentration within the wafer may decrease at a higher rate when the dopant is nearer the surface of the wafer. For example, dopant concentration in ultra shallow implants can be particularly prone to reduction due to out-diffusion.
A non-uniform temperature distribution across the wafer during an anneal cycle can lead to non-uniform dopant activation, non-uniform out-diffusion rates, as well as other deleterious effects that may cause asymmetric activation of the dopant to occur. Thus, an initially uniform dopant distribution may not necessarily produce uniform electrical properties across the wafer after anneal. This can be measured, for example, by sheet resistance (Rs) maps. Generally, the temperature gradients across a wafer during annealing tend to be radial, with the center of the wafer being slightly hotter than the edges. When this occurs, it can result in radial variations in the electrically activated dopant distribution profiles as shown in FIG. 7.
According to the methods and systems described herein, a method of compensating for anneal non-uniformities may comprise implanting dopant in a pattern to provide higher dopant concentrations where the anneal non-uniformities result in lower electrically active dopant concentrations. A pattern for the anneal non-uniformities may be determined by annealing a wafer having a uniform dopant distribution and measuring properties of the wafer after annealing, e.g., by obtaining a sheet resistance map of the wafer. In one embodiment, the non-uniformities may be measured by measuring temperature variations during annealing. The beam current density across the beam and the pass angle of the wafer through the beam may be adjusted to obtain the pattern for implanting the dopant. Computer readable medium may contain instructions to control a wafer implanter to implement the method.
A system for compensating for anneal non-uniformities may comprise means for determining the anneal non-uniformities, means for designing an implant pattern providing higher dopant concentrations where the anneal non-uniformities result in lower active dopant concentrations and means for implanting dopant in the implant pattern. The system may include means for annealing a sample wafer and means for measuring the properties of the sample wafer after annealing, such as by measuring sheet resistance. In one embodiment, means for measuring temperature variations during annealing may determine the anneal non-uniformities.
In one embodiment, the system may comprise a sensor to determine anneal non-uniformity data, a processor to design the implant pattern based on the anneal non-uniformity data and a controller to control the implantation of the wafer to implant dopant in the implant pattern designed. The sensor may measure sheet resistance, or alternately, may measure temperature variations during annealing. The controller may adjust the beam current density across the beam and/or the pass angle of the wafer through the beam.